Logo of Huzzle

Home

Matches

Explore

Manage

ANALOG LAYOUT :3 TO 6 YEARS BENGALURU, COIMBATORE & HYDERABAD

image

Capgemini Engineering

1mo ago

  • Job
    Full-time
    Mid & Senior Level
  • Engineering
    IT & Cybersecurity

AI generated summary

  • You need 3-6 years in mixed-signal layout design, proficiency in EDA tools, and experience with critical analog blocks and technologies down to 7nm. Strong debugging and communication skills are essential.
  • You will design analog layouts, optimize floorplans, debug LVS/DRC, understand layout effects, and implement high-quality designs for various blocks, ensuring timely execution and effective communication.

Requirements

  • Experience in Mixed-Signal layout design, holding bachelor’s degree
  • To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications.
  • Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
  • Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.
  • Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
  • Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Ability to understand design constraints and implement high-quality layouts.
  • Multiple Tape out support experience will be an added advantage.
  • Good people skills and critical thinking abilities to resolve the issue technically, and professionally.
  • Excellent communication. Responsible for timely execution with high quality of layout design.
  • Analog Layout
  • Process or technology experience: TSMC – 7nm, 5nm, 10nm, 28nm, 45nm, 40nm
  • EDA Tools:
  • Layout Editor: Cadence Virtuoso L, XL
  • Physical verification: DRC, LVS, Calibre
  • IO layout

Responsibilities

  • To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications.
  • Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
  • Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.
  • Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
  • Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Ability to understand design constraints and implement high-quality layouts.
  • Multiple Tape out support experience will be an added advantage.
  • Good people skills and critical thinking abilities to resolve the issue technically, and professionally.
  • Excellent communication. Responsible for timely execution with high quality of layout design.

FAQs

What is the experience required for this position?

The position requires 3 to 6 years of experience in analog layout design, specifically in mixed-signal layout design.

What educational background is needed for this role?

A bachelor’s degree in a relevant field is required for this position.

What type of layout design will I be working on?

You will be working independently on block-level analog layout design, which includes tasks like estimating area, optimizing floorplan, routing, and verifications.

What specific analog blocks will I be designing?

You will have firsthand experience in designing critical analog blocks such as temperature sensors, SerDes, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps, current mirrors, comparators, and differential amplifiers.

Which EDA tools should I be familiar with for this job?

Familiarity with EDA tools such as Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must.

Is experience with lower technology nodes necessary?

Yes, experience with lower technology nodes like 14nm FinFET and below, along with good LVS/DRC debugging skills, is essential.

What are the primary skills required for this role?

The primary skills required include analog layout expertise, experience with TSMC processes (7nm, 5nm, 10nm, 28nm, 40nm, 45nm), and proficiency in EDA tools for layout editing and physical verification.

Are there any additional skills that would be advantageous for this job?

Yes, experience with IO layout would be considered a secondary skill that is advantageous for this position.

What kind of work culture can I expect at Capgemini Engineering?

Capgemini Engineering promotes a diverse and responsible work culture, offering opportunities to work with a global team of engineers and scientists in a dynamic environment.

What is the company’s mission regarding technology and transformation?

Capgemini is focused on helping organizations accelerate their transition to a digital and sustainable world while creating tangible impacts for enterprises and society.

Is there support for multiple tape-out experiences in this role?

Yes, having multiple tape-out support experience will be an added advantage for candidates applying for this position.

What is expected in terms of communication skills for this job?

Excellent communication skills are essential as you will be responsible for timely execution with high quality of layout design and for resolving issues technically and professionally.

image

Capgemini Engineering

Capgemini Engineering, the leader in engineering and R&D services, helps clients unleash their R&D potential.

Technology
Industry
10,001+
Employees

Mission & Purpose

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has 60,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet. Capgemini Engineering is an integral part of the Capgemini Group, a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of €22.5 billion.