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Staff Design Verification Engineer

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Analog Devices

2mo ago

  • Job
    Full-time
    Expert Level
  • Engineering
    IT & Cybersecurity
  • Cork
  • Quick Apply

AI generated summary

  • You need 10-15 years in ASIC design verification, strong UVM/System Verilog skills, debug expertise, scripting proficiency, and experience with HW emulation. Leadership and communication skills are essential.
  • You will verify complex designs using advanced methods, develop UVM testbenches, manage verification scripts, debug GLS, mentor juniors, and support post-silicon verification activities.

Requirements

  • Verification of complex designs and sub-systems using leading edge verification methodologies
  • Contribute and influence the decisions on methodologies/strategies to be adopted for the verification. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
  • Architect the testbench and develop in UVM or Formal based verification approaches.
  • Proficient in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration.
  • Define test-plans, tests, and verification methodology for block/chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
  • Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
  • Continuous interaction with analog co-sim and firmware team.
  • Managing scripts written in TCL/Perl/Python for different verification aspects.
  • Coding up in C tests on M3 Series Cortex based products.
  • Topics of interest: processor architectures, DSP, power sequences, DC-DC converters, low power design, memory interfaces...
  • Technically mentor and guide junior verification engineers on SoC Verification.
  • Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team.
  • Bachelor’s or master’s degree, in Engineering (Electronic Engineering) or equivalent
  • Excellent debugging and analytical skills.
  • 10-15 years in ASIC design verification.
  • Experience with HW emulation or FPGA prototyping
  • Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing.

Responsibilities

  • Verification of complex designs and sub-systems using leading edge verification methodologies
  • Contribute and influence the decisions on methodologies/strategies to be adopted for the verification. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
  • Architect the testbench and develop in UVM or Formal based verification approaches.
  • Proficient in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration.
  • Define test-plans, tests, and verification methodology for block/chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
  • Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
  • Continuous interaction with analog co-sim and firmware team.
  • Managing scripts written in TCL/Perl/Python for different verification aspects.
  • Coding up in C tests on M3 Series Cortex based products.
  • Topics of interest: processor architectures, DSP, power sequences, DC-DC converters, low power design, memory interfaces...
  • Technically mentor and guide junior verification engineers on SoC Verification.
  • Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team.

FAQs

What is the primary responsibility of the Staff Design Verification Engineer at Analog Devices?

The primary responsibility of the Staff Design Verification Engineer is to lead the verification processes for complex digital systems, from the concept phase through design, implementation, and release, while collaborating with various technical teams within the company.

What qualifications are required for the Staff Design Verification Engineer position?

A Bachelor’s or Master’s degree in Engineering (Electronic Engineering) or equivalent is required, along with 10-15 years of experience in ASIC design verification, excellent debugging and analytical skills.

What verification methodologies should candidates be familiar with?

Candidates should have strong knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion-based and formal verification techniques with System Verilog, as well as the ability to architect testbenches and develop using UVM or formal verification approaches.

Is experience with hardware emulation or FPGA prototyping necessary for this role?

Yes, experience with hardware emulation or FPGA prototyping is one of the required qualifications for the position.

Will the Staff Design Verification Engineer have opportunities to mentor junior engineers?

Yes, part of the responsibilities includes technically mentoring and guiding junior verification engineers on SoC Verification.

What are the topics of interest for this position?

Topics of interest include processor architectures, DSP, power sequences, DC-DC converters, low power design, and memory interfaces.

What programming skills are necessary for this role?

Candidates need to be proficient in developing scripts in TCL/Perl/Python for various verification aspects and coding in C for tests on M3 Series Cortex-based products.

What benefits does Analog Devices offer its employees?

Analog Devices fosters a culture of equal opportunity and provides various benefits, but specific benefits are not detailed in the job description; interested candidates should inquire further during the application process.

Is travel required for this position?

Yes, the position requires some travel, estimated at about 10% of the time.

What is the working shift for this role?

The Staff Design Verification Engineer position is a first-shift days role.

Does Analog Devices take diversity and inclusion seriously in hiring?

Yes, Analog Devices is an equal opportunity employer and fosters a culture where everyone has the opportunity to succeed regardless of various backgrounds and characteristics.

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Analog Devices

Global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge

Manufacturing & Electronics
Industry
10,001+
Employees
1965
Founded Year

Mission & Purpose

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.