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Test Chip Design Integration Engineer

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Intel Corporation

Apr 27

Applications are closed

  • Job
    Full-time
    Entry Level
  • Software Engineering
  • Austin

Requirements

  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
  • Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
  • Minimum Qualifications:
  • Candidate must possess a MS degree with 6+ months of experience in Electrical Engineering or related field.
  • Experience above in SoC Integration, pre-Si validation, post-Si pattern generation and testing, including:
  • Micro-architecture and design features.
  • Behavioral modeling, Verilog/System Verilog coding.
  • RTL Synthesis, LEC, Automated Place and Route and Static Timing Analysis.
  • UPF (Unified Power Format) validation using low power techniques and handling multiple power domain design.
  • Simulation and testing of Analog and Mixed-signal circuits.
  • JTAG and other industry-standard protocols, state machines, memory logic design and verification.
  • Preferred Qualifications:
  • 6+ months of experience in the following:
  • Pre-Si validation - creation of test plan, test bench and test case development, review and debug of test results, and review assertions to prevent illegal states.
  • Test bench creation to generate Post-Si test patterns and vectors.
  • Scripting languages (perl, tcl etc) to enhance automation in design, validation and testing.

Responsibilities

  • Performs integration of cell libraries, functional units, and partitions into subsystems or full chip SoC designs. Conducts the subsystem/full chip layout, integration, verification, and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architectures. Designs, develops, and innovates integration methodologies and flows to improve physical design convergence in domains such as layout, timing, clock tree, formal verification, signal integrity, IO, debug, power routing, noise reduction, reliability, and power and performance. Optimizes design to improve product level parameters such as power, frequency, and area. Collaborates with the design teams during the chip design lifecycle to drive signoff closure for tapeout and meets IP technical and delivery requirements.
  • This is an entry level position and compensation will be given accordignly.

FAQs

What does a Test Chip Design Integration Engineer do at Intel?

A Test Chip Design Integration Engineer at Intel is responsible for working on various facets of semiconductor manufacturing, including process development, manufacturing, yield improvement, packaging, final test and optimization, and Supply Chain support. They work in the Technology Development and Manufacturing Group to bring smart, connected devices to people around the world.

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Intel Corporation

Technology
Industry
10,001+
Employees
1968
Founded Year

Mission & Purpose

Intel’s mission is to shape the future of technology to help create a better future for the entire world. By pushing forward in fields like AI, analytics and cloud-to-edge technology, Intel’s work is at the heart of countless innovations. From major breakthroughs like self-driving cars and rebuilding the coral reefs, to things that make everyday life better like blockbuster effects and improved shopping experiences — they’re all powered by Intel technology. With a career at Intel, you have the opportunity to help make the future more wonderful for everyone.