FAQs
What is the primary focus of this internship?
The primary focus of this internship is on verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products as part of a mixed-signal design team.
What qualifications are required for the intern position?
The required qualifications include a solid understanding of digital circuit design, basic knowledge of C/C++ and RISC processors, hands-on experience in writing test cases in Verilog and System Verilog, and familiarity with scripting languages like Python or Perl in a Linux environment.
What are the desired skills for this internship?
Desired skills include knowledge of high-speed digital and mixed-signal design, familiarity with industry digital verification methodologies such as VMM/UVM, experience with version control systems like GIT/SVN/Perforce, and good organization and communication skills.
What tasks will the intern be responsible for?
The intern will be responsible for creating and updating test plans and test cases, writing modular constrained-random/coverage-driven Verilog and SystemVerilog testbenches, writing SystemVerilog assertions, monitoring simulation regressions, debugging RTL and Gate-level simulation failures, and tracking issues in Jira while documenting in Confluence.
Is previous experience in digital verification necessary?
While previous experience in digital verification is not explicitly required, a strong understanding of digital circuit design and hands-on experience with relevant tools and languages is important.
Where is this internship located?
This internship is located in Markham, Ontario, Canada.
What type of team will the intern be working with?
The intern will be working with a highly experienced mixed-signal design team, consisting of expert digital and mixed signal engineers.
What kind of tasks will the intern perform related to simulations?
The intern will be involved in writing functional coverage and performing functional/code/assertion coverage analysis, as well as monitoring simulation regressions and debugging issues related to both RTL and Gate level simulations.
Will the intern have opportunities for skill development?
Yes, the internship offers excellent opportunities for skill development by collaborating with an expert team and gaining hands-on experience in digital verification methods and practices.