Job

ASIC Design Verification Engineer, Machine Learning, University Graduate

Google

•

2mo ago

💼 Graduate Job

Sunnyvale

🤑 £105K - £152K

⌛ Closed

Applications are closed

Graduate Job

Data, Software Engineering•Sunnyvale

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a key member of the team, you manage projects in multiple areas with your expertise. You also monitor the performance of vendors working on projects and evaluate new technologies.
In this role, you will use your design and verification expertise to verify complex digital designs. You'll collaborate closely with design and verification engineers in active projects and perform direct verification. Using SystemVerilog coding and problem solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You'll be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.

Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
Academic, educational, internship, or project experience designing or verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs.
Experience coding in SystemVerilog or Verilog.
Preferred Qualifications:
Master's or Doctorate degree in Electrical Engineering or related field.
Experience with verification methodology such as UVM/OVM/VMM.
Experienced with the full verification life cycle.
Knowledge of SystemVerilog.
Strong problem solver, communicator, and team player.

Currently Studying

Masters

PhD

Data

Software Engineering

Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Work type

Full time

Work mode

office

Location

Sunnyvale

Salary

105000 - 152000 GBP