FAQs
What is the minimum educational qualification required for this role?
The minimum educational qualification required is a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
How many years of experience are needed for this position?
A minimum of 3 years of experience is required in digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
What programming skills are preferred for this role?
Excellent C/C++ programming and software design skills are preferred for this role.
Are there opportunities for individuals with advanced degrees?
Yes, a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, is preferred.
What types of projects will I be working on in this role?
You will be responsible for RTL design development of camera and machine learning designs, including RTL coding, architecture, power, performance, and area (PPA) optimizations.
What scripting languages are acceptable for this role?
Experience with scripting languages such as Perl or Python is acceptable for this role.
Will I be involved in verification processes?
Yes, you will perform RTL verification using industry-standard methodologies and participate in test planning and coverage analysis.
Is experience with ASIC design methodologies a requirement?
Yes, experience with ASIC design methodologies for clock domain checks and reset checks is preferred.
What is the work environment like at Google in this role?
You will be part of a diverse team that develops custom silicon solutions, contributing to innovation behind products powered by Google’s AI, software, and hardware technologies.
Does Google provide equal employment opportunities?
Yes, Google is committed to equal employment opportunity regardless of various factors, including race, gender identity, disability, and veteran status.